This invention relates to bi-directional signaling, and more particularly to improved methods and apparatuses for conducting and testing bi-directional signaling over a single transmission line.
In a typical integrated circuit testing configuration, test signals only travel in one direction at a given time between the tester and the integrated circuit. Such uni-directional signaling works well for integrated circuits with dedicated input or output pads/pins. However, many integrated circuits are configured with input/output (I/O) circuits that support bi-directional signaling through the same pad/pin. For example, certain memory integrated circuits include I/O circuits through which access is provided to the memory. As such, data can be written to the memory by providing (inputting) applicable signals to a pad/pin of an I/O circuit. The same pad/pin of the I/O circuit can be used to read data from the memory when the I/O circuit provides (outputs) a representative signal to the pad/pin. In certain implementations, the inputting and outputting of signals associated with the memory occur simultaneously.
Fully testing the operation of such integrated circuits can be difficult if not impossible, as the uni-directional tester will need to operatively switch the signaling direction back and forth between sending test signals to the integrated circuit and receiving test signals from the integrated circuit.
By way of example, FIG. 1 depicts a conventional uni-directional signaling testing arrangement 100 configured to support limited bi-directional signaling. Arrangement 100, in this example, includes a tester device 102 operatively coupled through a single transmission line 104 to a device under test (DUT) 106 (e.g., an integrated circuit). Here, to conduct limited bi-directional signaling over transmission line 104, tester device 102 and DUT 106 need to take turns in sending/receiving signals. Hence, this is essentially a time-multiplexed solution for conducting and testing bi-directional signaling.
As mentioned above, one of the drawbacks to testing arrangement 100 is that it is unable to conduct simultaneous bi-directional signaling. As such, DUT 106 may not be fully tested since only a portion of the operational I/O bandwidth can be tested. More specifically, the average bandwidth of transmission line 104 will be lower, because there is usually a need to pause between switching the direction of the signaling to allow the voltage in transmission line 104 to dissipate.
Hence, there is a need for arrangements that allow the full operational bandwidth to be tested.
As a basic reference, FIG. 2 depicts an exemplary receiver portion 120 of tester device 102. Here, receiver portion 120 includes a high gain comparator 122 that is configured to measure if the received signal from DUT 106 is above or below a threshold voltage level (VCMP). Comparator 122 outputs the measured voltage level (VRCV). Receiving circuits such as this and associated signal driving circuits are well known.
With this in mind, FIGS. 3a-b depict two common time-multiplexed testing arrangements and techniques. As shown in the example of FIG. 3a, tester device 102 includes a receiver portion represented by comparator 122, and a driver portion represented by operational amplifier 124. These portions are operatively configured to time-share transmission line 104. Here, since both the receiver and driver portions utilize the same transmission line 104, there is a need to pause transmissions when switching to allow earlier signals to propagate.
FIG. 3b depicts a slightly improved testing arrangement, wherein dual transmission lines are provided. Here, transmission line 104a is configured to carry signals from operational amplifier 124 to DUT 106; transmission line 104b is configured to carry signals from DUT 106 to comparator 122. Because of the separate transmission lines, there is no need to wait as long for propagation delays when switching between receiver and driver portions. While this reduces the turn around time delays, the performance of the DUT cannot be fully tested, because the transmission sequence still needs to be reversed (i.e. simultaneous bi-directional signaling is not supported).
There are some test circuits that allow for simultaneous bi-directional signaling. However, such circuits are configured for use with specific devices, such as telephone devices. By way of example, FIG. 4 depicts an exemplary arrangement for providing bi-directional signaling over two transmission lines 126. As shown, this arrangement includes similarly configured transceivers (identified as Transceiver A and Transceiver B) coupled together through transmission lines 126. Since this arrangement is common to telephony, the transmission lines are usually implemented using twisted pair wires. Although detailed analysis of this well known arrangement is beyond the scope of this document, a brief conceptual description is provided below. Readers seeking additional information are directed, for example, to a text by William J. Dally and John W. Poulton, Digital Systems Engineering, Section 8.3, published by Cambridge University Press, March 1998.
Conceptually, the arrangement in FIG. 4 is fairly simple in operation in that each transceiver is configured to subtract its outgoing signal from the incoming signal before sampling the data. Here, for example, in Transceiver A forward voltage Vfl (which includes transmitted data DTA) is subtracted from received voltage VLA using a comparator to produce received data DRA. Note, that both transceivers require VL(A,B) and VT (a threshold voltage) as carried through transmission lines 126.
Ensuring that a DUT having only has a single I/O pad/pin works correctly is less straightforward. The pin electronics in most conventional semiconductor testing equipment (e.g., automated testing equipment (ATE)) can only be configured to receive or transmit data at a given time, because the test equipment receiver lacks the second externally accessible port used to cancel any outgoing signal that is applied to the DUT (i.e., as in the exemplary arrangement in FIG. 4). As such, the standard configurations for testing I/O connections are unable to test simultaneous I/O because the tester driver will interfere with data seen at the tester receiver. One possible solution to this problem would be to redesign the tester. This would likely be a very expensive engineering endeavor, since testers tend to be very precise and carefully engineered devices; for example, an average semiconductor ATE device can cost in excess of one million dollars.
Consequently, there is a need for improved methods and apparatuses for conducting bi-directional signaling and testing devices that support such bi-directional signaling.